/*
-------------------------------------------------------------------------------------------  
  File       : tb_interface.sv 
  Author     : Rohit Kulkarni
  Description: Testbench for testing the parallel interface
-------------------------------------------------------------------------------------------
*/

parameter TRUE              = 1'b1;
parameter FALSE             = 1'b0;
parameter CLOCK_CYCLE       = 20;
parameter CLOCK_WIDTH       = CLOCK_CYCLE/2;
parameter slave_1_addr      = 8'h01;
parameter slave_2_addr      = 8'h02;
parameter DATA_WIDTH        = 8;
parameter data_to_write     = 8'hF0;

module tb_interface;
  
  reg clk;
  reg [DATA_WIDTH-1:0]  r_data;
  reg [DATA_WIDTH-1:0]  w_data;
  
  //Instantiate the unit under test (UUT)
  top TOP(.clk(clk));
  
/*
   Create free running clock
*/
initial
begin
  clk = FALSE;
  forever #CLOCK_WIDTH clk = ~clk;
end

/*
    Set up monitor
*/
initial
begin
  $display("                Time      rb  wb     slave_addr    data             ack\n");
  $monitor($time, "     %b   %b       %b       %b          %b", TOP.bus.rb, TOP.bus.wb, TOP.bus.slave_addr, TOP.bus.data, TOP.bus.ack);
end
 
/*
    Generate stimulus
*/
initial
begin
  repeat (6) @(negedge clk);
  TOP.bus.MasterRead(slave_1_addr, r_data);
  TOP.bus.CheckParity(r_data); 
  repeat (6) @(negedge clk);
    
  TOP.bus.MasterWrite(slave_2_addr, data_to_write);
  TOP.bus.GenerateParity(data_to_write, 1'b0);
  repeat (6) @(negedge clk);

  TOP.bus.MasterWrite(slave_1_addr, data_to_write);
  TOP.bus.GenerateParity(data_to_write, 1'b0);
  repeat (6) @(negedge clk);

  TOP.bus.MasterRead(slave_2_addr, r_data);
  TOP.bus.CheckParity(r_data); 
  repeat (6) @(negedge clk);

  $stop;
end  
  
  
endmodule


